To obtain a high brightness and high efficient light emitting diode (LED) for general illumination, it may be desirable to fabricate a vertical light emitting diode (VLED) having a light emitting structure sandwiched between two electrodes. Recently, major LED manufacturers have commercialized VLED chips. The majority of these conventional VLEDs are produced by transferring the LED structure initially formed on a sapphire substrate to a conducting substrate using a laser lift-off process. Some manufacturers have also recently claimed to have achieved white LEDs with luminous efficacy of 150 lm/W (lumens per watt) using vertical LEDs and phosphors. In addition, there have been studies on GaN on silicon which show that vertical LEDs can also be achieved by transferring LED structures grown on bulk silicon (Si) substrates to conducting substrates by wafer bonding or chemical lift-off processes. However, the internal quantum efficiency (IQE) of the LED structure on bulk Si is lower due to the high density of threading dislocations.
Various conventional approaches have been disclosed in an attempt to increase the light extraction efficiency of conventional VLEDs, such as roughening (e.g., by forming photonic crystals) or patterning the top surface of the LED structure. However, a major problem with such conventional approaches relates to chip handling when roughening or patterning the top surface of the LED structure after the layer transfer process (i.e., after the LED structure has been transferred to a conducting substrate). For example, roughening the surface by dry or wet etching using a high temperature deposition process would likely cause cracking of the transferred LED structure due to a vertical stress gradient created by the thermal expansion mismatch between the transferred LED structure and the conducting substrate. In addition, expensive techniques such as electron beam lithography result in a low throughput fabrication process. On the other hand, simple dry etching to roughen the top surface of the LED structure (e.g., by aggressive reactive ion etching or plasma etching) does increase light output but results in poor light extraction efficiency due to the lack of ordering or regularity in the patterns formed on the top surface. For example, the roughened surface may be damaged by the plasma etch and possesses a high density of point defect complexes (such as vacancy-impurity complexes).
Conventionally, GaN-based LED structure formed on a sapphire substrate requires the removal of expensive sapphire substrate through laser lift-off (LLO) in the commercial production of high brightness LEDs. This conventional method is costly as it requires the use of high power lasers and expensive large area sapphire substrates. The sapphire substrate production is also commercially limited to 6 inch wafer size and hence, growth potential to larger substrate sizes is limited. Furthermore, the use and maintenance of high power lasers are complicated and difficult to control resulting in non-uniform yield from wafer to wafer during the laser lift of large diameter wafer. Since sapphire substrates are insulators, heat dissipation is also a major concern for flip-chip LEDs. On the other hand, the growth of GaN-based LED structure on bulk Si or SOI is cost effective and may lead to a higher manufacturing yield. However, the internal quantum efficiency (IQE) of the LED structure on bulk Si is lower due to a higher defect density.
A need therefore exists to provide a vertical light emitting diode (VLED) and a method of fabricating the VLED which seek to overcome, or at least ameliorate, one or more of the above deficiencies associated with the conventional VLEDs, and in particular, to enhance the light extraction efficiency of the VLED. It is against this background that the present invention has been developed.